1. Field of the Invention
This invention relates to a semiconductor storage device to achieve simplification of the screening of defective memory cells in probing tests.
2. Description of Related Art
FIG. 7 is a figure showing in summary an example of the configuration of the principal parts of dynamic RAM (hereafter called xe2x80x9cDRAMxe2x80x9d) comprising a sense amp.
The DRAM shown in FIG. 7 comprises a first and second memory cell array (MCBLKl and MCBLKr), and one sense amp 10.
The two memory cell arrays (MCBLKl and MCBLKr) and the sense amp 10 are connected by a bit line pair comprising two bit lines, indicated by BL and /BL.
In these DRAM memory cell arrays MCBLKl and MCBLKr, numerous word lines intersect with this bit line pair (BL and /BL), and memory cells are connected to these intersections.
In FIG. 7, four word lines (WLlm, WLln, WLrm and WLrn), and a first through a fourth memory cell (12, 14, 16 and 18), are shown.
The sense amp 10 is connected to a sense amp driving line SAen to activate the sense amp 10.
A first and second transistor T1 and T2 are provided between the sense amp 10 and the memory cell array MCBLKl. The gate electrodes of these transistors (T1 and T2) are connected to a transfer gate control line TGl. The channel of the transistor T1 is provided on the bit line BL, and the channel of the transistor T2 is provided on the bit line /BL.
Between the sense amp 10 and the memory cell array MCBLKr are provided a third and fourth transistor T3 and T4. The gate electrodes of these transistors (T3 and T4) are connected to a transfer gate control line TGr. The channel of the transistor T3 is provided on the bit line BL, and the channel of the transistor T4 is provided on the bit line /BL.
First to third bit line equalizer circuits (20, 22 and 24), including equalizer lines (EQMl, EQMr and EQS), are connected to BL and /BL.
Between BL or /BL, and the data buses DB or /DB, are provided a fifth and sixth transistor (T5 and T6) which control these connections.
A column select line CL is connected to the gates of these transistors (T5 and T6).
FIG. 8 is a figure showing an example of the configuration of a conventional semiconductor storage device, and is used to explain signal outputs of signal lines the names of which appear in FIG. 7 (TGl, TGr, EQMl, EQMr, EQS).
The signal output circuit shown in FIG. 8 comprises first, second and third NOT gates (26, 28 and 30), series-connected in order, which take the output voltage level from the memory cell select signal line BSl which selects the memory cell as the output voltage level of the equalizer line EQMl; fourth, fifth and sixth NOT gates (32, 34 and 36), series-connected in order, which take the output voltage level from the memory cell select signal line BSr as the output voltage level of the equalizer line EQMr; a circuit in which are series-connected a first NAND gate 38 and a seventh NOT gate 40, in this order, which takes the output voltage level from the memory cell select signal lines (BSl and BSr), after passing through the first and fourth NOT gates 26 and 32 respectively, as the output voltage level of the equalizer line EQS; a first transfer gate control line control unit 44, comprising seventh through 14th transistors (T7, T8, T9, T10, T11, T12, T13, T14) and an eighth NOT gate 42, which takes the output voltage level from the memory cell select signal line BSl as the output voltage level of the transfer gate control line TGl; and, a second transfer gate control line control unit 48, comprising 15th through 22nd transistors (T15, T16, T17, T18, T19, T20, T21, T22) and a ninth NOT gate 46, which takes the output voltage level from the memory cell select signal line BSr as the output voltage level of the transfer gate control line TGr.
In FIG. 8, 50 and 52 are first and second high-potential voltage output units, which output high voltages (Vcc+Vt+xcex1 (where Vcc is the power supply voltage, Vt is a threshold voltage, and xcex1 greater than 0)), constantly input from outside, to the first and second transfer gate control line control units.
The first transfer gate control line control unit 44 is connected to the connection point of the NOT gates 26 and 28, to the output points of the NOT gates 28 and 34, and to the output point of the first high-voltage output unit 50. The second transfer gate control line control unit 48 is connected to the connection point of the NOT gates 32 and 34, to the output points of the NOT gates 34 and 28, and to the output point of the second high-voltage output unit 52.
Next, the operation during data readout (zero (0) readout) of the DRAM shown in FIG. 7 and FIG. 8 is explained.
FIG. 9 is an operating waveform diagram employed in this explanation, indicating the operating waveforms during zero (0) readout from memory cells.
At time t0 (initial state), both of the above two DRAM memory cell arrays (MCBLKl and MCBLKr) are in the unselected state, and the signal levels of the memory cell select signal lines (BSl and BSr), which select the memory cell for data readout, are both at the low logical level, that is, the xe2x80x9clowxe2x80x9d state (this state corresponds to a binary xe2x80x9c0xe2x80x9d, and hereafter is denoted xe2x80x9cLxe2x80x9d).
From FIG. 8, the levels of the equalizer signals output at this time by the equalizer lines (EQMl, EQMr and EQS) are at the logical high level, that is, the xe2x80x9chighxe2x80x9d state (this state corresponds to a binary xe2x80x9c1xe2x80x9d, and is hereafter denoted xe2x80x9cHxe2x80x9d), and each of the bit lines BL and /BL is precharged to the (xc2xd)Vcc level (where Vcc is the power supply voltage).
At time t1, the signal level of the memory cell select signal line BSl which controls the selected memory cell array MCBLKl changes from the xe2x80x9cLxe2x80x9d state to the xe2x80x9cHxe2x80x9d state. This is accompanied by a change in the level of the equalizer signal output from the equalizer lines (EQMl and EQS) from the xe2x80x9cHxe2x80x9d state to the xe2x80x9cLxe2x80x9d state.
Hence equalization of the bit lines BL and /BL of the selected memory cell array MCBLKl stops, and so each of the bit lines enters a floating state while being maintained at a potential of (xc2xd)Vcc.
Also at this time, the level of the equalization signal output from the equalizer line (EQMr) goes to the xe2x80x9cHxe2x80x9d state, and equalization of the bit lines BL and /BL of the unselected memory cell array MCBLKr is maintained.
Then, at time t2, the output voltage from the transfer gate control line TGl between the selected memory cell array MCBLKl and the sense amp 10 becomes Vcc+Vt+xcex1 (where Vt is a threshold value, and xcex1 greater than 0).
Further, the transfer gate control line TGr between the unselected memory cell array MCBLKr and the sense amp 10 goes to GND level (for a reason explained below).
Hence the gates of the transistors (T1 and T2) are turned on, and the line between the selected memory cell array MCBLKl and the sense amp 10 becomes conducting. On the other hand, the gates of the transistors T3 and T4 are turned off, and the line between the unselected memory cell array MCBLKr and the sense amp 10 is in the non-conducting state.
Next, at time t3, one of the word lines (here, assumed to be WLlm) is selected, and the output voltage from this word line (WLlm) goes to the level Vcc+Vt+xcex1 (where Vt is a threshold value, and xcex1 greater than 0) (word line voltage increase).
At time t4, the information written to the memory cell (here, shown by 12) selected by the selected word line (WLlm) is output as a potential difference xcex94V to the bit line (here BL). At this time, the voltage of the bit line /BL is at the (xc2xd)Vcc level.
Then, at time t5, the sense amp enable signal output from the sense amp driving line SAen changes from the xe2x80x9cLxe2x80x9d state to the xe2x80x9cHxe2x80x9d state, and in response the sense amp 10 is activated.
Through the sensitivity amplification action of the activated sense amp 10, the potential of the bit line BL is pulled up to Vcc, and the potential of the bit line /BL is lowered to GND level.
Next, at time t6 the level of the column select line CL changes from the xe2x80x9cLxe2x80x9d to the xe2x80x9cHxe2x80x9d state, and in response the potential difference of the bit lines BL and /BL is generated on the data buses DB and /DB, so that the bit line information (until now, the information zero (0)) is read on the data buses.
According to reference (1) (ULSI DRAM Gijutsu, Science Forum, Takao Nakano and Yoichi Akasaka, editors, pp. 37-38), in reading data (either xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) written to a memory cell, the potential change xcex94V in the bit line at the time of reading from a xe2x80x9cone transistor plus one capacitorxe2x80x9d-type memory cell is expressed by the following equations. At this time, the precharge level of the bit lines (BL and /BL) is in both cases (xc2xd)Vcc (where Vcc is the power supply voltage).
xcex94V(1)=(Vcc/2)/(1+Cb/Cs)xe2x80x83xe2x80x83(1) 
xcex94V(0)=(Vcc/2)/(1+Cb/Cs)xe2x80x83xe2x80x83(2) 
Here Cs is the memory cell capacitance, and Cb is the stray capacitance of the bit line. From the above equations (1) and (2), xcex94V depends on the ratio Cb/Cs of Cb and Cs.
In configuring the DRAM, it is preferable that Cb/Cs be made as small as possible, to ensure an adequate signal voltage difference xcex94V for detection by the sense amp, in order to prevent malfunction of the sense amp.
This is because, in a configuration in which xcex94V is small, the sense amp sensitivity may be inadequate; or, even for a voltage difference xcex94V that can be sensed by the sense amp, there is a greater possibility that normal sensitivity amplification action may not occur, or that the sense amp may otherwise malfunction.
Hence in the above-described explanation of DRAM operation, the setting of the voltage level from the transfer gate control line TGr to GND level is in order to reduce Cb as much as possible and ensure an adequate xcex94V, by employing a configuration in which the line capacitance (Cb) of the bit lines BL and /BL of the memory cell array MCBLKr, which is unselected, is not considered.
In the past, in manufacturing such semiconductor storage devices (DRAM), electrical characteristic tests (probe tests and similar) to confirm operation as a semiconductor device are performed after completion of wafer processes.
In these probe tests, a voltage is applied to the pad (electrode) portions on the semiconductor wafer, the electrical characteristics of the tested circuit are inspected, and the inspection results are used to judge the quality of the device.
These probe tests are used to screen memory cells, and redundancy replacement and other processing of defective memory cells extracted in this process is performed.
In performing screening, rewriting of the data contents written to memory cells, and various tests to judge the quality when writing data differing from that of neighboring memory cells, are performed.
This is performed because normally, a defective memory cell among memory cells positioned in extremely close proximity may erroneously pass a test, without its defective nature being discriminated, due to the influence of peripheral memory cells (through coupling or similar).
Hence various tests must be performed in order to execute more rigorous screening, and so there are concerns that such tests will require increased time and costs.
Hence a technical method for resolving the above problems has been sought.
One object of this invention is to provide a semiconductor storage device for which screening can be performed using probe tests which are simpler than in the prior art.
In order to achieve this object, the semiconductor storage device of this invention has the following configuration features. That is, the semiconductor device comprises a bit line pair, comprising a first and second bit line each connected to a plurality of memory cells, and a sense amp and control circuit connected by this bit line pair.
Through control signals output from this control circuit, the semiconductor storage circuit causes the first and second bit lines between the sense amp and the memory cells connected to the sense amp to be in the non-conducting state during normal operation, and causes these bit lines to be in the conducting state during characteristic tests.
By this means, it is possible to appropriately switch the connection state of the bit lines between the sense amp and the memory cells to which the sense amp is connected, during probe tests or other electrical characteristic tests and during normal operation.